1. Field of the Invention
The present invention relates to a bipolar memory cell and, more particularly, to a bipolar memory cell having capacitors and Schottky-barrier diodes (hereafter referred to as SBD).
2. Description of the Prior Art
FIG. 15 is an equivalent circuit diagram showing one memory cell, which includes a bipolar memory. The bipolar memory cell consists of a flip-flop circuit using two bipolar transistors 51, 52 in which a base b1 is connected to a collector n2 of the transistor 52 and an upper word line W1 through a parallel connecting object having a resistor r2, a SBD d2 and a capacitor c2. A base b2 of the transistor 52 is connected to a collector n1 of the transistor 51 and the word line W1 through a parallel connecting object having a resistor r1, a SBD d1 and a capacitor c1. The transistors 51, 52 have two emitters, respectively. One emitter e1d of the transistor 51 is connected to a digit line D1, the other emitter e1h thereof is connected to a lower word line W2. One emitter e2d of the transistor 52 is connected to a digit line D2, the other emitter e2h thereof is connected to the word line W2.
For example, as prior art of the bipolar memory cell, a device structure is disclosed in "SOFT-ERROR CHARACTERISTICS IN BIPOLAR MEMORY CELLS WITH SMALL CRITICAL CHARGE" by Y. Idei et al. in VLSI Symposium circuit, pp. 27-28, 1989. FIG. 14A shows a plane diagram showing a semi-device region of the bipolar memory cell and FIG. 14B is a sectional diagram along an E--E line of the divided FIG. 14A. In general, to form the memory cell the two device regions shown in FIG. 14A are connected by wirings. An N.sup.+ type buried layer 42 is formed on a P type semiconductor substrate 41, an N.sup.- type epitaxial layer 43 is formed on the buried layer 42. Further, the substrate 41 is divided into multiple device regions. The epitaxial layer 43 comprises a base region 46 having two emitter regions 47, high density N type region extending from a capacitor forming region 49 near the substrate surface to the N.sup.+ type buried layer 42, and a platinum silicide layer near a surface of an SBD forming region 48. Moreover, a dielectric film (tantalum pentoxide) may be formed on the high density N type region of the capacitor forming region 49. A barrier metal film is formed on the dielectric film, and extended to a surface of the platinum silicide of the SBD forming region 48. Therefore, a capacitor and an SBD are constructed, respectively.
There is a problem that the bipolar memory cell having the SBD is affected by the so-called soft-error, easily. That is, the flip-flop state is inverted by a current through the OFF-state SBD, for example, in response to a noise current caused by an alpha ray incidence. To solve this problem, it has been considered to increase a junction capacitance by extending the SBD forming region 48, so that the soft-error occurrence may be controlled desirably. However, this causes difficulty in realizing high integration of a semiconductor device. To solve this, the prior art described above proposes to increase the soft-error tolerance by connecting the capacitor formed by using ferroelectric material with the SBD.
Recently, considering the high integration of a semiconductor device, a new bipolar memory cell is desirable which enables further high integration of the semiconductor device. The bipolar memory cell of the prior art described above has a problem in that reduction in the SBD forming region 49 causes a decrease in the soft-error tolerance. Otherwise, a large-capacity capacitor is required to reduce the SBD forming region 49 and maintain the soft-error tolerance. However, an increase in the capacitor capacitance results in a requirement for an expansion of the capacitor forming region 49, and high integration of the semiconductor device is difficult.
Therefore, an object of the present invention is to provide a novel bipolar memory cell which is characterized by a superior soft-error tolerance, and is suitable for a highly integrated memory device.